The invention relates to a sample-and-hold circuit comprising:
an input terminal for the application of an input signal to be sampled, PA1 a first buffer stage having an input coupled to the input terminal, and having an output, PA1 a first switching element having a control electrode coupled to a clock signal terminal for the application of a clock signal, having a first main electrode coupled to the output of the first buffer stage, and having a second main electrode, PA1 a first capacitive impedance having a first terminal coupled to the second main electrode of the first switching element, and having a second terminal coupled to a point of fixed potential, PA1 an output amplifier having a non-inverting input coupled to the first terminal of the first capacitive impedance, having an inverting input, and having an output coupled to an output terminal for supplying a sampled output signal, PA1 a second switching element having a control electrode coupled to the clock signal terminal, having a first main electrode coupled to the output of the output amplifier, and having a second main electrode coupled to the inverting input of the output amplifier, and PA1 a second capacitive impedance having a first terminal coupled to the second main electrode of the second switching element and having a second terminal coupled to the output of the output amplifier. PA1 a second buffer stage having an input coupled to the point of fixed potential and having an output coupled to the second terminal of the first capacitive impedance, PA1 a third buffer stage having an input coupled to the output of the output amplifier, and having an output coupled to the first main electrode of the second switching element, and PA1 a fourth buffer stage having an input coupled to the output of the output amplifier, and having an output coupled to the second terminal of the second capacitive impedance.
Sample-and-hold circuits, also referred to as track-and-hold circuits, are frequently used as interface circuits from the time-continuous domain to the time-discrete domain and vice versa. Examples can be found in analog-to-digital converters and digital-to-analog converters and in switched capacitor circuits.
A sample-and-hold circuit of the type defined in the opening paragraph is known inter alia from Japanese Kokai No. 55-8656(A). The input signal to be sampled is buffered by the first buffer stage, which charges the first capacitive impedance to the instantaneous value of the input signal when the first switch element is turned on. The output amplifier is arranged as a voltage follower and serves as a buffer between the first capacitive impedance and the output terminal. The output amplifier receives negative feedback by means of the second switching element and the second capacitive impedance, which are arranged in parallel between the output and the inverting input.
When the first switching element is conductive the output signal is a scaled replica of the input signal, the input signal being subjected to a filtering process which is dependent on the impedances of the first switching element and on the first capacitive impedance. When the first switching element is turned off charge carrriers are injected towards the impedances connected to the first and the second main electrode of the first switching element. This injection produces an undesired voltage step across the first capacitive impedance, which step also appears in the output signal. This effect is known as clock feedthrough. Said voltage step is counteracted by means of the second switching element and the second capacitive impedance in the negative-feedback path of the output amplifier. These elements produce a voltage step at the inverting input, which serves to compensate for the voltage step produced at the non-inverting input by the first semiconductor switch. However, this compensation is not perfect because the impedances connected to the first and second main electrodes of the first and the second switching element are not entirely equal to one another. Therefore, the attainable reduction of the clock feedthrough is liable to improvement.